Methods for fabricating anode shorted field stop insulated gate bipolar transistor

ABSTRACT

A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

FIELD OF THE INVENTION

This invention relates to methods for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT).

BACKGROUND OF THE INVENTION

Insulated gate bipolar transistors (IGBT) are three-terminal power semiconductor devices. The IGBT combines the simple gate-driven characteristics of a metal-oxide-semiconductor field effect transistor (MOSFET) with the high current, low saturation voltage capability of bipolar transistors. This is accomplished by combining an isolated gate FET, which serves as the control input of the IGBT, with a bipolar transistor, which serves as the switch for the IGBT, in a single device.

FIG. 1A is a cross-sectional schematic diagram illustrating a conventional IGBT according to the prior art. A conventional IGBT comprises a field stop layer 103 of n-type supported by a p+ substrate 101. An n− epitaxial/voltage blocking layer 105 is grown on top of the field stop layer 103. One or more cells can be formed with the epitaxial/voltage blocking layer 105. Each cell may include a p-type body region 107 formed within the epitaxial/voltage blocking layer 105 and one or more n+ emitter regions 109 formed within the p-type body region 107. Each cell may further include gate electrode insulator 111 (e.g., an oxide) formed on an exposed part of the p-type body region 107 and n+ emitter regions 109. A gate electrode 113 is formed on the gate insulator 111. Emitter electrodes 115 are formed on different portions of the body region 107 and emitter region 109. A collector electrode 117 can be formed on a back surface of the p+ substrate 101. The IGBT 100 is constructed similarly to an n-channel vertical MOSFET, except that the n+ drain is replaced with a p+ collector layer 101, thus forming a vertical PNP bipolar junction transistor. The additional p+ collector layer 101 creates a cascade connection of a PNP bipolar junction transistor with the surface n-channel MOSFET.

The IGBT provides more optimal performance in certain applications over a conventional MOSFET device. This is mainly due to the fact that the IGBT exhibits a significantly lower forward voltage drop in comparison to the MOSFET. However, the increase in forward voltage drop is off-set by the slow switching speeds of the IGBT device. Minority carriers that are injected into the n− epitaxial/voltage blocking layer 105 take time to enter and exit or recombine at turn on and turn off, resulting in longer switching times and higher switching losses in comparison to the MOSFET.

In response to the slow switching speeds of conventional IGBT devices, anode-shorted IGBT devices have been developed. The anode-shorted IGBT is superior to the conventional IGBT in that it exhibits more desirable switching characteristics while retaining the improved forward voltage drop. FIG. 1B is a cross-sectional schematic diagram illustrating a conventional anode-shorted IGBT in accordance with the prior art. The anode-shorted IGBT 100′ shown in FIG. 1B is essentially the same as the IGBT in FIG. 1A, except that the p+ substrate 101 in FIG. 1A is replaced by a layer consisting of alternating p-type regions 101 and n-type regions 119 in FIG. 1B. By alternating p-regions 101 and n-type regions 119 the IGBT is effectively provided an additional body diode as well as improved switching speeds.

Embodiments of the present invention relate to methods for fabricating such an anode-shorted insulated gate bipolar transistor (IGBT).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional schematic diagram illustrating a conventional insulated gate bipolar transistor (IGBT) according to the prior art.

FIG. 1B is a cross-sectional schematic diagram illustrating a conventional anode-shorted insulated gate bipolar transistor (IGBT) according to the prior art.

FIGS. 2A-2H are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to an embodiment of the present invention.

FIGS. 3A-3F are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to an alternative embodiment of the present invention.

FIGS. 4A-4H are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to another alternative embodiment of the present invention.

FIG. 5A-5I are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to another alternative embodiment of the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

For convenience, use of + or − after a designation of conductivity or charge carrier type (p or n) refers generally to a relative degree of concentration of designated type of charge carriers within a semiconductor material. In general terms an n+ material has a higher negative charge carrier (e.g., electron) concentration than an n material and an n material has a higher carrier concentration than an n− material. Similarly, a p+ material has a higher positive charge carrier (e.g., hole) concentration than a p material and a p material has a higher concentration than a p− material. It is noted that what is relevant is the concentration of charge carriers, not necessarily dopants. For example, a material may be heavily doped with n-type dopants but still have a relatively low charge carrier concentration if the material is also sufficiently counter-doped with p-type dopants. As used herein, a concentration of dopants less than about 10¹⁶/cm³ may be regarded as “lightly doped” and a concentration of dopants greater than about 10¹⁷/cm³ may be regarded as “heavily doped”.

FIGS. 2A-2H are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated bipolar transistor (IGBT) according to an embodiment of the present invention. The fabrication method begins with a lightly doped p− substrate 201 as shown in FIG. 2A. A masked implant (mask not shown) is performed on the top surface of the substrate 201 in order to selectively form a plurality of first semiconductor regions 203 of a first conductivity type within a top surface of the substrate 201 as shown in FIG. 2B. By way of example, and not by way of limitation, the first conductivity type may be n+. The first semiconductor regions 203 may then be diffused to a desired depth. In some applications, it is preferable to diffuse the first semiconductor regions to a depth of at least 10 μm. In other applications, a width of the first semiconductor regions may be much smaller than a space between adjacent first semiconductor regions to minimize any snapback issues of the finished device.

After the one or more first semiconductor regions 203 have been formed, a field stop layer 205 of the first conductivity type may be grown onto the top surface of the substrate 201 as shown in FIG. 2C. The field stop layer 205 may have a lower concentration of charge carriers than the first semiconductor regions 203. By way of example, and not by way of limitation, the field stop layer 205 may be n type doped. An epitaxial/voltage blocking layer 207 of the first conductivity type may then be grown on top of the field stop layer 205 as illustrated in FIG. 2D. The voltage blocking layer 207 may have a lower concentration of charge carriers than the field stop layer 205.

One or more IGBT component cells 209 may then be formed on a top portion within the epitaxial/voltage blocking layer 207 as shown in FIG. 2E. The term “IGBT component cell” as defined herein will refer to a cell that includes a body region, one or more emitter regions, a gate electrode, one or more corresponding emitter electrodes, and insulating layers. While an IGBT component cell must include those particular components, one ordinarily skilled in the art will recognize that several different configurations may exist for implementing those IGBT components. For example, the IGBT in FIG. 1A illustrates one possible configuration for implementing an IGBT component cell including emitter regions formed within body regions and an insulated gate. The IGBT component cells 209 formed within the epitaxial/voltage blocking layer 207 may be any configuration so long as they comprise the components discussed above and retain their functionality.

The back surface of the substrate 201 is then thinned, e.g., by Taiko grinding, to a desired thickness such that the first semiconductor regions 203 are exposed as shown in FIG. 2F. The term “Taiko grinding” as used herein refers to a process of grinding an inner surface of a wafer while leaving an outer edge on the outermost circumference untouched. This method reduces the risk of thin wafer handling and lowers warping of the wafer during device processing. For certain applications, it is desirable to grind the back surface of the substrate 201 to a thickness of 5 μm an below the field stop layer 205.

A blanket implant of a second conductivity type is then performed on the back surface of the substrate 201, resulting in implant regions 211 being formed within the back surface of the substrate 201 as shown in FIG. 2G. By way of example, and not by way of limitation, the implant regions may be doped p+ type. Also by way of example, and not by way of limitation, the blanket implant may be a Boron implant with a doping concentration of 1×10¹⁶ cm⁻³ performed at an energy level of 40 KeV. The blanket implant is limited to minimal activation because the high temperatures (typically 900-1000 degree C. for 30 minutes) required to fully activate the implant regions 211 would destroy the IGBT cells 209. Because of the limited activation of the blanket implant, the first semiconductor regions 203 are unaffected by the p+ implant.

Lastly, metal 213 may be evaporated onto the back surface of the substrate 201 to form the collector electrode of the IGBT as shown in FIG. 2H. This process may be performed at 450° C. thereby partially activating the implant regions 211. The resulting structure is an anode-shorted field stop IGBT, with alternating p regions 201, 211 and n regions 203 forming the anode short circuit.

In this embodiment, the p+ regions 211 are implanted from the back at the end of the process, allowing accurate control of the injection efficiency of the IGBT without compromise to the IGBT field stop characteristics of positive temperature coefficient, fast switch without lifetime control and no increase in turn off energy E_(off) with temperature. Further the p+ implant is carried out without a mask. This allows the wafer to be ground to a much thinner degree to reduce on resistance compare to the existing technology that uses masking process simply because masking would be difficult on a thin wafer.

FIGS. 3A-3F are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to an alternative embodiment of the present invention. The fabrication method begins with an epitaxial/voltage blocking layer 303 that is formed on a very lightly doped substrate 301. The substrate and epitaxial layer may be doped with opposite conductivity types. By way of example, and not by way of limitation, the blocking layer 303 may be doped to be n− type and the substrate 301 may be doped p− type. One or more IGBT component cells 304 may then be formed within the epitaxial/voltage blocking layer 303 as shown in FIG. 3B. As noted above, the term “IGBT component cell” refers to a cell that includes a body region, one or more emitter regions, a gate electrode, one or more corresponding emitter electrodes, and insulating layers in any suitable/functional configuration, such as that shown in FIG. 1A.

The substrate 301 may be thinned, e.g., by grinding, to a desired thickness. A blanket implant of a the first conductivity type may then be performed to the back surface of the epitaxial/voltage blocking layer 301 to form a field stop layer 305 as shown in FIG. 3C. The field stop layer 305 may have a higher concentration of charge carriers than the blocking layer 301. By way of example, and not by way of limitation, the field stop layer 305 may be doped to be n type. Also by way of example and not by way of limitation, the blanket implant may be a Phosphorous implant with a doping concentration of 1-2×10¹³ cm⁻³ performed at an energy level ranging between 100-300 KeV.

A first shadow-masked (mask not shown) implant is then performed on a back surface of the field stop layer 305 to selectively form one or more first semiconductor regions 307 of a second conductivity type within the back surface of the field stop layer 305 as shown in FIG. 3D. The term “shadow mask” refers to a metal mask with patterned holes that may directly contact a wafer or may be remotely positioned in proximity to the wafer in order to form a desired pattern within or on top of the wafer. By way of example, and not by way of limitation, the first semiconductor regions 307 may be p+ type doped. Also by way of example, and not by way of limitation, the first shadow-masked implant may be a Boron implant with a doping concentration of 1×10¹⁶ cm⁻³ performed at an energy level of 40 KeV.

A second shadow-masked (mask not shown) implant is then performed on the back surface of the field stop layer 305 to selectively form one or more second semiconductor regions 309 of the first conductivity type within the back surface of the field stop layer 305 as shown in FIG. 3E. The second semiconductor regions 309 may be doped more heavily than the blocking layer 301 and field stop layer 305. By way of example and not by way of limitation, the second semiconductor regions 309 may be n+ type doped. Also by way of example and not by way of limitation, the second shadow-masked implant may be a Phosphorous implant with a doping concentration of 1×10¹⁶ cm⁻³ performed at an energy level of 40 KeV. The first semiconductor regions and the second semiconductor regions may then be laser activated. Laser activation is a process that involves directing a high-energy laser pulse at a desired location. Because of its short duration, the laser pulse activates the dopants without reaching the front surface of the device structure and damaging the IGBT component cells 303.

Lastly, metal 311 may be deposited onto the back surface of the first and second semiconductor regions 307, 309 to form the collector electrode of the IGBT as shown in FIG. 3F. By way of example and not by way of limitation, the metal 311 may be an aluminum-tin-nickel-silver (Al—Ti—Ni—Ag) alloy. The resulting structure is an anode-shorted field stop IGBT, with alternating p regions 307 and n regions 309 forming the anode short circuit. The use of two masks avoids counter-doping the heavy doped regions as described in process shown in FIG. 2G. In one embodiment the first shadow mask and the second shadow mask are complementary. In another embodiment a width of the semiconductor regions of the second conductivity type 307 is much larger than a width of the semiconductor regions of the first conductivity type 309.

FIGS. 4A-4H are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to another alternative embodiment of the present invention. The fabrication method begins with an epitaxial/voltage blocking layer 403 formed on a substrate 401 as shown in FIG. 4A. The substrate and epitaxial layer may be of the same conductivity type but with different concentrations of charge carriers. By way of example, and not by way of limitation, the substrate 401 may be n+ type and the epitaxial layer 403 may be n-type. One or more IGBT component cells 404 may then be formed the epitaxial/voltage blocking layer 403 as shown in FIG. 4B. As noted above, the term “IGBT component cell” refers to a cell that includes a body region, one or more emitter regions, a gate electrode, one or more corresponding emitter electrodes, and insulating layers in any suitable/functional configuration.

The back surface of the epitaxial/voltage blocking layer 401 is then thinned, e.g. by Taiko grinding, to a desired thickness. As discussed above, the term “Taiko grinding” refers to a process of grinding an inner surface of a wafer while an outer edge on the outermost circumference remains untouched (not shown). A blanket implant of the first conductivity type is then performed to the back surface of the substrate 401 to form a field stop layer 405 as shown in FIG. 4C. The field stop layer 405 may have a higher concentration of charge carriers than the blocking layer 403 and a lower concentration of charge carriers than the substrate 401. By way of example, and not by way of limitation, the field stop layer 405 may be n type doped if the substrate 401 is n+ doped and the blocking layer 403 is n− doped. Also by way of example and not by way of limitation, the blanket implant may be a phosphorous implant with a doping concentration of 1-2×10¹³ cm⁻³ performed at staggered energies ranging up to 1 MeV in order to achieve a field stop layer 405 of several microns.

A blanket implant of the second conductivity type is performed to a back surface of the field stop layer 405 in order to form a first implant layer 407 of the second conductivity type within the back surface of the field stop layer 405 as shown in FIG. 4D. By way of example, and not by way of limitation, the first implant layer 407 may be p+ doped. Also by way of example and not by way of limitation, the blanket implant may be a boron implant with a doping concentration of 1×10¹⁶ cm⁻³ performed at an energy level of 40 KeV.

The dopants in the first implant layer 407 and field stop layer 405 may then be laser activated. As noted above, laser activation is a process that involves directing a high-energy laser pulse at a desired location. Because of their short duration, laser pulses do not penetrate into the front surfaces of the device structure.

After the first implant layer 407 and field stop layer 405 have been laser activated, a first metal layer 409 (e.g., an aluminum layer of 5000 Å) is deposited onto a backside of the first semiconductor layer 407 as shown in FIG. 4E. Isolated implant regions 407′ may then be selectively formed by laser cutting one or more portions of the first metal layer 409 and first semiconductor layer 407 such that one or more portions of the field stop layer 405 are exposed as shown in FIG. 4F.

A blanket implant of dopants of the first conductivity type is then performed to the exposed portions of the field stop layer 405 using the patterned first metal layer 409 as a mask in order to form second implant regions 411 within exposed portions of the field stop layer 405 between isolated implant regions 407′ as shown in FIG. 4G. The isolated implant regions 407′ are shielded from exposure to the blanket implant by the first metal layer 409. The second semiconductor regions 411 may be doped to have a higher concentration of charge carriers than the blocking layer 403 and the field stop layer 405. By way of example, and not by way of limitation, the second implant regions 411 may be doped n+ type if the blocking layer is doped n− and the field stop layer is doped n type. Also by way of example and not by way of limitation the blanket implant may be a phosphorous implant with a doping concentration of 1×10¹⁶ cm⁻³ performed at an energy level of 40 KeV. A second metal layer 413 may then be deposited over the first and second semiconductor regions 407′ and 411 as shown in FIG. 4H. By way of example, and not by way of limitation, the second metal layer 413 may be a titanium-nickel-silver (Ti—Ni—Ag) alloy. Prior to depositing the second metal layer 413 a sputter etch may be performed on the second metal layer 409 to remove any oxide formed on the first metal layer 409 due to exposure to the external environment. The second metal layer 413 and first metal layer 409 collectively form the collector electrode of the IGBT device. The resulting structure is an anode-shorted field stop IGBT, with alternating p implant regions 407′ and n implant regions 405 forming the anode short circuit.

The metal layers 409 and 413 can be different types of metals specifically chosen for their ability to make good contact with the differently doped implant regions 407′, 411. For example first the implant regions 407′ may be doped p+ type and the second implant regions 411 may be doped n type or n+ type. Aluminum makes good contact to p type regions and titanium makes good contact to n type or n+ type regions. In such a case, the first metal layer 409 may be Aluminum and the second metal layer 413 may be Titanium. The resulting structure provides good electrical contact to both implant regions 407′, 411. In addition, cutting an aluminum layer into pieces during the patterning process may reduce stress due to the differences in coefficient of thermal expansion (CTE) between Al and the underlying substrate material (e.g., Silicon).

FIG. 5A-5J are cross-sectional schematic diagrams illustrating a method for manufacturing an anode-shorted field stop insulated gate bipolar transistor (IGBT) according to another alternative embodiment of the present invention. The fabrication method begins with a substrate 501 as shown in FIG. 5A. By way of example, and not by way of limitation, the substrate 501 may be an n+ type substrate. By way of example, and not by way of limitation, the substrate 501 may have a thickness of approximately 700 μm. A first epitaxial layer 503 of the same conductivity type as the substrate is formed on a top surface of the substrate 501 as shown in FIG. 5B. The first epitaxial layer 503 is a semiconducting material of the same conductivity type as the substrate 501 but with a lower concentration of charge carriers than the substrate. By way of example, and not by way of limitation, the first epitaxial layer 503 may be n− type doped if the substrate 501 is doped n+ type. Also by way of example and not by way of limitation, the first epitaxial layer may have a thickness of approximately 10 μm.

After the first epitaxial layer 503 is formed, a field stop layer 505 may be formed on top of the first epitaxial layer 503 as shown in FIG. 5C. The field stop layer 505 is a semiconducting layer of the same conductivity type as the substrate and first epitaxial layer. The field stop layer has a charge carrier concentration that is greater than that of the first epitaxial layer 503 and less than that of the substrate 501. By way of example, and not by way of limitation, the field stop layer 505 may be n type doped if the substrate 501 is n+ type doped and the first epitaxial layer 505 is n− type doped. Also by way of example and not by way of limitation, the field stop layer 505 may have a thickness of approximately 5 μm. A second epitaxial layer 507 of the same conductivity type as the substrate 501, first epitaxial layer 503, and field stop layer 505 is then grown on top of the field stop layer 505 as shown in FIG. 5D. The second epitaxial layer 507 is sometimes referred to herein as the voltage blocking layer 507. The second epitaxial layer 507 may have a lower charge carrier concentration than the substrate 501 and the field stop layer 505. Again, by way of example, and not by way of limitation, the voltage blocking layer 507 may be n− type doped if the substrate 501 is n+ type doped, the first epitaxial layer 503 is n− type doped, and the field stop layer 505 is n type doped. Also, by way of example, and not by way of limitation, the voltage blocking layer may be approximately 100 μm for a 1200V IGBT device or approximately 50 μm for a 600V device.

One or more IGBT component cells 509 may then be formed within a top surface of the voltage blocking layer 507 as shown in FIG. 5E. As noted above, the term “IGBT component cell” refers to a cell that includes a body region, one or more emitter regions, a gate electrode, one or more corresponding emitter electrodes, and insulating layers in any suitable/functional configuration. Following formation of the IGBT component cells 509 the substrate 501 is thinned to a desired thickness by removing material from a back side of the substrate as shown in FIG. 5F. The substrate 501 may be thinned, e.g., by grinding it from the back side. For certain applications, the desired thickness of the substrate 501 after grinding is approximately 5 μm.

A masked metal deposition is then performed on the back surface of the substrate 501 to form a metal pattern 511 on the back surface of the substrate 501 as illustrated in FIG. 5G. The masked deposition may be implemented using a shadow mask, similar to the one discussed above. An anisotropic etch (e.g., a wet etch) may then be performed on the substrate 501 using the metal pattern 511 as a mask, so that one or more portions of the first epitaxial layer 503 are exposed, while leaving portions of the substrate 501 under the metal pattern as shown in FIG. 5H. For certain applications, the desired etch-depth may be approximately 10 μm, depending on the thickness of the substrate remaining after thinning.

A backside blanket implant is then performed on the substrate 501 to implant dopants of an opposite conductivity type to that of the substrate 501, field stop layer 505, and epitaxial layer 503, 507 into exposed portions of the first epitaxial layer 503 and the substrate 501. The dopant implant forms implant regions 513 as shown in FIG. 5I. An annealing process may then be completed to activate the implant regions 513. By way of example and not by way of limitation, if the substrate 501, field stop layer 505, and epitaxial layers 503, 507 are doped n+, n, and n− type, respectively, the implant regions may be doped p+ type.

Lastly a metal layer 511′ is deposited onto a back surface of the implant regions 513 and a back surface of the metal pattern 511 in order to form a collector electrode for the IGBT device. The resulting structure is an anode-shorted field stop IGBT, with alternating semiconductor regions of opposite conductivity type formed by the implant regions 513 and remaining portions of the substrate 501 forming the anode short circuit.

While the above is a complete description of the preferred embodiments of the present invention, it is possible to use various alternatives, modifications, and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A” or “An” refers to a quantity of one or more of the items following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for”. Any element in a claim that does not explicitly state “means for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 USC §112, ¶ 6. 

1. A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising: a) selectively forming first semiconductor regions of a first conductivity type within a top surface of a semiconductor substrate, wherein the first conductivity type is opposite a conductivity type of the substrate; b) growing a field stop layer of the first conductivity type onto the top surface of the substrate, wherein the field stop layer has a lower concentration of charge carriers than the first semiconductor regions; c) growing an epitaxial layer of the first conductivity type on top of the field stop layer, wherein the epitaxial layer has a lower concentration of charge carriers than the field stop layer; d) forming one or more insulated gate bipolar transistors (IGBT) component cells within the epitaxial layer; e) thinning a back surface of the substrate to a desired thickness and expose the first semiconductor regions; f) performing a blanket implant to form implant regions of a second conductivity type opposite that of the epitaxial layer and field stop layer within the back surface of the substrate; and g) evaporating metal onto the back surface of the substrate.
 2. The method of claim 1, wherein the substrate is a p− type substrate.
 3. The method of claim 2, wherein the first semiconductor region is doped n+, the field stop layer is doped n and the epitaxial layer is doped n−.
 4. The method of claim 3, wherein the implant regions are doped p+.
 5. The method of claim 1, wherein forming the first semiconductor regions comprises performing a masked implant followed by diffusion.
 6. The method of claim 5, wherein the first semiconductor regions are diffused at least 10 μm into the top surface of the substrate.
 7. The method of claim 1, wherein the desired thickness in e) is 5 μm below the field stop layer.
 8. The method of claim 1, wherein the blanket implant in f) is a Boron implant with a concentration of 1e16 performed at 40 keV.
 9. The method of claim 1, wherein g) is performed at 450° C.
 10. A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising: a) forming one or more insulated gate bipolar transistors (IGBT) component cells within a top surface of an epitaxial layer of a first conductivity type; b) thinning a back surface of the epitaxial layer to a desired thickness; c) performing a blanket implant of the first conductivity type to the back surface of the epitaxial layer to form a field stop layer, wherein a concentration of charge carriers in the field stop layer is greater than that of the epitaxial layer; d) selectively implanting first semiconductor regions of a second conductivity type that is opposite the first conductivity type within a back surface of the field stop layer using a first shadow mask, wherein a concentration of charge carriers in the first semiconductor regions is greater than that of the field stop layer; e) selectively implanting second semiconductor regions of the first conductivity type within a back surface of the field stop layer using a second shadow mask, wherein a concentration of charge carriers in the second semiconductor regions is greater than that of the field stop layer; and f) laser activating the first and second semiconductor regions; g) depositing a metal layer to a back surface of the first and second semiconductor regions.
 11. The method of claim 10, wherein the epitaxial layer is doped n−, the field stop layer is doped n, the first semiconductor regions are doped p+ and the second semiconductor regions are doped n+.
 12. The method of claim 11, wherein the first shadow mask and the second shadow mask are complementary.
 13. The method of claim 11, wherein a width of the first implant regions of the second conductivity type is much larger than a width of second semiconductor regions of the first conductivity type.
 14. The method of claim 10, wherein the blanket implant in c) is a Phosphorous implant with a concentration between 1×10¹³/cm³ and 2×10¹³/cm³ performed at 100-300 keV.
 15. A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising: a) forming one or more insulated gate bipolar transistors (IGBT) component cells within a top surface of an epitaxial layer of a first conductivity type; b) thinning a back surface of the epitaxial layer to a desired thickness; c) performing a blanket implant of the first conductivity type to the back surface of the epitaxial layer to form a field stop layer, wherein a charge carrier concentration of the field stop layer is greater than that of the epitaxial layer; d) performing a blanket implant of a second conductivity type that is opposite the first conductivity type to a back surface of the field stop layer to form first semiconductor implant regions; e) laser activating the field stop layer and first semiconductor layer; f) depositing a first metal layer to a backside of the first semiconductor layer; g) selectively forming isolated semiconductor implant regions by laser cutting through one or more portions of the first metal layer and the first semiconductor implant region to expose one or more portions of the field stop layer; h) performing a blanket implant of the first conductivity type to the exposed portions of the field stop layer form second semiconductor implant regions within the exposed portions of the field stop layer, wherein a charge carrier concentration of the second semiconductor implant regions is greater than that of the field stop layer; i) depositing a second metal layer on the first metal layer and exposed portions of the second semiconductor implant regions.
 16. The method of claim 18, wherein the epitaxial layer is doped n−, the field stop layer is doped n and the second semiconductor regions are doped n+.
 17. The method of claim 20, wherein the first semiconductor layer is doped p+.
 18. The method of claim 21, wherein the first metal layer makes good contact with the first semiconductor implant regions and the second metal layer makes good contact with the second semiconductor implant regions.
 19. A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising: a) forming a semiconducting first epitaxial layer on a top surface of a semiconducting substrate, wherein the first epitaxial layer and substrate are of the same conductivity type and the first epitaxial layer has a lower concentration of charge carriers than the substrate; b) forming a semiconducting field stop layer on top of the first epitaxial layer, wherein the field stop layer is of the same conductivity type as the substrate and first epitaxial layer, wherein the field stop layer has a higher concentration of charge carriers than the first epitaxial layer and a lower concentration of charge carriers than the substrate; c) forming a semiconducting second epitaxial layer on top of the field stop layer, wherein the field stop layer is of the same conductivity type as the substrate, first epitaxial layer, and field stop layer, wherein the second epitaxial layer has a lower concentration of charge carriers than that of the substrate and field stop layer; d) forming one or more insulated gate bipolar transistors (IGBT) component cells in the second epitaxial layer; e) thinning the substrate to a desired thickness by removing material from a back side of the substrate; f) forming a metal pattern on a back surface of the substrate; g) performing an anisotropic etch on the back side of the substrate using the metal pattern as a mask, wherein the anisotropic etch exposes one or more portions of the first epitaxial layer; h) performing a backside blanket implant of dopants into the exposed portions of the first epitaxial layer to form implant regions, wherein the implant regions are of an opposite conductivity type to that of the substrate, first epitaxial layer, field stop layer, and second epitaxial layer; i) forming a metal layer on the back surface of the first semiconductor regions the metal pattern.
 20. The method of claim 19, wherein the substrate is doped n+ type, the first epitaxial layer is doped n− type, the field stop layer is doped is n type.
 21. The method of claim 20, wherein the second epitaxial layer is doped n− type
 22. The method of claim 20, wherein the implant regions are doped p+ type. 